Nvidia's 2028 Chip Is Already Rearranging TSMC's Fabs

Reports on August 14, 2026 describe Nvidia shifting research and supply-chain resources toward Feynman, its post-Rubin platform, while Vera Rubin is still entering mass production. Feynman is scheduled for 2028 and expected to combine TSMC's 2nm-class A16 process, 3D chiplets via SoIC, custom HBM, and co-packaged optics.

TSMC's response is visible in concrete. The foundry is accelerating construction at AP7 in Chiayi and AP8 in the Southern Taiwan Science Park, preparing capacity for SoIC, CoWoS-L, and next-generation CoPoS.

A chip two years from tape-out is already determining where a foundry pours foundations. That is the story.

Packaging became the constraint, and nobody voted on it

For thirty years, the interesting question in semiconductors was the transistor. How small, how fast, how leaky. Packaging was the boring step at the end where you glued the die to a substrate.

That inverted. The binding constraint on an AI accelerator is no longer how many transistors you can print — it is how much silicon and memory you can wire together into one coherent package at acceptable yield and thermals.

Which is why the Feynman spec reads the way it does. A16 is the process node, and it gets one line. The rest of the list is assembly: 3D stacking through SoIC, custom high-bandwidth memory, and optical interconnect moved into the package itself. Reports also point to NVLink bandwidth potentially exceeding 1 petabyte per second as Nvidia scales cluster sizes.

None of that is transistor scaling. All of it is integration.

CoPoS is the part that changes the shape

CoWoS — chip-on-wafer-on-substrate — has carried the entire AI accelerator industry, and it has a hard geometric ceiling: it is built on a round wafer, and a round wafer wastes area at the edges once your package gets large enough.

CoPoS moves the interposer onto a rectangular panel. Rectangles tile without waste. That is the whole idea, and it is the sort of unglamorous manufacturing change that quietly resets what is buildable — because the size limit on a package is what determines how much compute and memory can sit inside one accelerator.

Reports indicate TSMC is pulling CoPoS toward a 2028 production window, and separately that it has revised SoIC plans to meet demand from Nvidia and AMD, targeting roughly 50,000 wafers per month by late 2027.

Two facilities and a process transition, sequenced to land with one customer's 2028 product.

What it means that Nvidia can do this

Consider the counterfactual. A smaller accelerator company, however good its architecture, cannot cause a foundry to accelerate building construction and reprioritize a packaging roadmap. It gets allocated whatever capacity remains after the anchor customers are served.

Nvidia can, and reportedly has advanced packaging lines booked years out. That produces a compounding advantage that has nothing to do with chip design: the company that shapes the manufacturing roadmap gets to design for capabilities that will exist, while everyone else designs for capabilities they hope to be allocated.

This is the most durable moat in the business and the least discussed one. Architectural leads erode — competitors copy good ideas within a generation or two. Supply-chain co-design does not erode, because it is a relationship with a physical asset base that takes years and tens of billions to replicate.

It also means the interesting Nvidia risk is not "someone builds a faster GPU." It is anything that disrupts the flow between Santa Clara and Taiwan.

Three simultaneous demand curves

The important detail in the reporting is that demand is no longer only CoWoS. SoIC, CoWoS-L, future CoPoS, and CPO-related technologies all have to scale at once.

That is a materially harder industrial problem than expanding one process. Each technology has distinct equipment, distinct yield learning curves, distinct materials supply, and distinct trained-labor requirements. Running four expansions in parallel means four chances to be the bottleneck, and the slowest one sets the ceiling for everybody.

It also means the 2027–2028 supply picture is less predictable than the headline capex figures suggest. Capital expenditure buys buildings and tools. It does not buy yield, and advanced packaging yield on a new panel format is the sort of thing that arrives late and then arrives all at once.

The read

Three practical conclusions.

Nvidia's roadmap is now a supply-chain artifact, not just a design one. Feynman's feasibility depends less on architectural cleverness than on whether AP7 and AP8 come online with working CoPoS. Watch the construction and the yield reports, not the keynote.

The 2028 accelerator will be defined by package size and optics, not by node. A16 is table stakes. What differentiates is how much silicon and memory fits in one package and how fast light moves between them.

Everyone else is scheduling around Nvidia's calendar. When a foundry accelerates two facilities to meet one customer's 2028 part, every other customer's roadmap becomes a function of the leftover capacity — and the leftover capacity is set by how well that one part sells.

The chip does not exist yet. The buildings for it are going up anyway.